This invention relates generally to memory error detection systems for computing systems, and more particularly to memory error detection systems that provide array entry duplication for hard error detection.
High performance microprocessors typically include logic to improve performance. In one example, microprocessors include a branch history table (BHT) that stores a direction history of recently encountered branch instructions. Many processors also include a Branch Target Buffer (BTB) that stores branch address and target address bits associated with the given branch. The BHT and the BTB are used by prediction logic to predict the direction (take vs. not taken) and the target address of the branch instruction. The BHT and BTB are implemented as either a register file or an array.
At least two types of errors can occur in these performance related register files or arrays. A soft error is a seemingly random inversion of stored data. This inversion may be caused by occasional electrical noise, environmental conditions and, in some cases, by bombardment of radioactive particles, the so-called alpha-particle event. In contrast, a hard error represents a permanent electrical failure of the memory array, often restricted to a particular memory location but may also sometimes be associated with peripheral circuitry of the memory array so that the entire array can be affected.
Unlike most arrays on the microprocessor, it is possible for there to be an error in the performance array and the error goes unnoticed. For example, the error from a BHT can simply look like a “bad prediction.” A “bad prediction” is a natural occurring event because it is only a prediction and hence is handled in the microprocessor through means to compare a prediction versus an actual outcome and take appropriate measures should the prediction be incorrect.
Conventional methods of detecting such errors include implementing ECC/parity bits in the array to allow for an ECC/parity check upon reading the data content out. A parity bit on the index can also be stored within the array to verify the content read out correlates with the entry which was indexed.
Depending on the size of the array or register files, these additional bits per entry can significantly increase memory usage. It would be desirable to be able to detect errors within the performance enhancing arrays or register files while minimizing memory usage.